Random access memories (RAMs) are now widely used in computers and other electronic devices. Today, the digital circuit designer has at his or her disposal a wide variety of RAMs of different types and sizes. Generally, the factors used to select a particular RAM for a particular application include price, power consumption, access speed, integrated circuit (IC) chip size and reliability.
For applications requiring a fairly large amount of memory at a minimal cost, dynamic complementary metal oxide semiconductor (CMOS) memory is typically a good compromise. Dynamic memory cells occupy minimal bit cell area, thereby minimizing IC cost, but require circuitry for continuously providing "refresh" cycles necessary to maintain the integrity of the memory content.
On the other hand, if access speed and data integrity are of primary concern, CMOS static RAM (SRAM) memory is a better choice. A static bit cell typically occupies a larger area than a dynamic bit cell on an IC, resulting in higher cost, but is generally easier to use because a static bit cell can maintain its memory content without being refreshed. Other advantages of SRAM memory include faster data access times and reduced power consumption in low frequency applications.
FIG. 1a shows the r.sup.th bit cell of the c.sup.th column of a prior art static memory IC having a total of C columns and R rows. FIG. 1b shows an example of a conventional row address decoder for an embodiment of the memory shown in FIG. 1a having sixteen rows of memory. Conventionally, "columns" and "rows" refer to the physical layout of the memory cell array. However, the memory is accessed logically as 8-bit, 16-bit or 32-bit words. For example, a 2K.times.8 memory has 16,384 memory cells typically arranged in an array of 128 columns and 128 rows, and is typically accessed eight bits at a time, so that a user has 2,048 words, each word being eight bits wide.
Referring again to FIG. 1a, the r.sup.th memory bit cell 100 of the C.sup.th column is shown in greater detail and has a bit output node 120 and a complementary bit output node 130. N-channel field effect transistors (FETs) Q3 and Q4 are coupled to their respective load resistors R1 and R2 which act as internal cell pull-up loads. The gate of FET Q3 is coupled to the drain of the opposing FET Q4 and vice versa. Together, the cross-coupled transistors Q3 and Q4 and load resistors R1 and R2 are responsible for maintaining the logic state of bit cell 100 and thereby retaining bit cell data against any leakage current.
In this configuration, one of FETs Q3 and Q4 is normally ON while the opposing FET is OFF. Bit cell 100 has two stable states, HIGH and LOW. Either state, can be overridden by applying an appropriate sequence of external signals in a write cycle, described in greater detail below. These two stable states provide bit cell 100 with the desired characteristic of a static memory cell.
In the above described static RAM configuration, data is written into and read from each memory cell via a differential pair of bit lines BIT and BIT. In the storage mode, the voltages on a row select lead and node 110 and a column select lead and node 210 are normally LOW, thereby keeping bit transmission gates Q1, Q2 and column transmission gates 201, 202 OFF.
Pull-up N-channel FETs 301 and 302 of column pull-up circuit 300 are always ON, thereby keeping bit lines BIT and BIT normally HIGH when the bit lines are not coupled to a bit cell in column c. Pull-up FETs 301 and 302 are needed due to the low static pull-up current supplied by load resistors R1 and R2. The static pull-up currents supplied by load resistors R1 and R2 are in the range of 5 pA to 500 nA in a typical SRAM cell. If pull-up FETs 301 and 302 were not provided, a leakage current flowing through bit cell 100 due to a charge associated with the stray capacitance of one of bit lines BIT and BIT near ground potential may unintentionally flip the state of bit cell 100.
Prior to a read operation, due to the low pull-up current in static bit cell 100, column pull-up FETs 301 and 302 of column pull-up circuit 300 are needed to pull the voltages of both bit lines BIT and BIT towards V.sub.DD to prevent an excessive differential voltage from developing between bit lines BIT and BIT. Pull-up circuit 300 can be implemented using other schemes including but not limited to resistors, N-channel transistors, or P-channel transistors, while serving the function of providing a limited conductance connection between bit lines BIT, BIT and the V.sub.DD supply.
Hence, pull-up circuit 300 comprising FETs 301 and 302 functions in a manner similar to pull-up load resistors (i.e. FETS 301 and 302 are always on). In other words, when bit output node 120 and complementary bit output node 130 are coupled to bit lines BIT and BIT, respectively, one of the bit lines BIT or BIT will contend with one of FETS 301 and 302. During a read cycle, because FETS 301 and 302 form high impedance connections to V.sub.DD, one of bit output nodes 120 or 130 of bit cell 100 will pull (force) the source of either FET 301 or 302 to a low level. Similarly, when bit cell 100 is being written, the high writing current produced by one of data lines DATA and DATA will pull the source of either FET 301 or 302 to a low voltage level.
A read cycle of bit cell 100 is as follows. As described above, when there are no read or write operations in progress, bit lines BIT and BIT are normally HIGH due to pull-up circuit 300. If bit cell 100 is in the HIGH state (i.e., bit output node 120 is HIGH and complementary bit output node 130 is LOW) pulling row select lead and node 110 HIGH turns both bit transmission gates Q1 and Q2 ON, thereby coupling bit output node 120 and complementary bit output node 130 to bit lines BIT and BIT, respectively. In addition, increasing the voltage on column select lead and node 210 serves to turn both column transmission gates 201 and 202 ON, thereby coupling bit lines BIT and BIT to data bus lines DATA and DATA, respectively. As a result, the HIGH voltage level on bit output node 120, together with the complementary LOW level on complementary bit output node 130, are now transmitted onto data bus lines DATA and DATA, respectively.
A write HIGH cycle of bit cell 100 begins with asserting the desired logic level and its complement onto data bus lines DATA and DATA, respectively. Placing a logic level HIGH onto column select lead and node 210 turns both column transmission gates 201 and 202 ON. If DATA is HIGH and DATA is LOW, this has the effect of pulling bit line BIT LOW while leaving bit line BIT HIGH. Similarly, driving row select lead and node 110 HIGH turns both bit transmission gates Q1 and Q2 ON. When bit transmission gate Q1 turns ON, bit output node 120 of bit cell 100 (which is coupled to the gate of FET Q4) is pulled HIGH, thereby turning FET Q4 ON. Similarly, when bit transmission gate Q2 turns ON, complementary bit output node 130 of bit cell 100 (which is coupled to the gate of FET Q3) is pulled LOW, thereby turning FET Q3 OFF. Thus bit output node 120 is now set to a HIGH level and complementary bit output node 130 is set to a LOW level at the end of this write cycle when the voltage on the row select line 110 is returned to its normal LOW logic level.
A write LOW cycle of bit cell 100 is very similar because the static RAM memory cell circuitry is substantially symmetrical. Bit output node 120 is set to a LOW logic level and complementary bit output node 130 is a HIGH logic level at the end of the write LOW cycle. This is done by placing LOW and HIGH logic level signals on DATA and DATA, respectively, at the start of the write LOW cycle. During write operations, due to higher current supplied via data bus lines DATA and DATA, bit line voltages typically go lower in voltage than they do in read operations or when the columns are not being addressed (i.e., in a "deselected" state).
If a manufacturing defect exists such that there is a leakage in bit transmission gates Q1 or Q2 from an internal node of bit cell 100 to bit lines BIT or BIT, then an extended write operation (write of a long duration) on the c.sup.th column to any one of the other rows (rows 1 to (r-1) and (r+1) to R) can cause the data of bit cell 100 to be corrupted or lost. This is because an extended write to any bit cell other than cell 100 of the c.sup.th column provides a current leakage path for an adequate length of time into cell 100 via bit lines BIT and BIT to affect the contents of cell 100. Note that this particular leakage problem does not occur when cell 100 is being read and when cell 100 is in the deselected state, because bit cell 100 is designed to be stable under these conditions.
Further, if one of transistors Q1 and Q2 is not just leaky but rather is completely shorted, then a write and subsequent read operation is sufficient to identify the complete short defect by detecting the inability of cell 100 to latch a logic state and then maintain that logic state during the read operation. Hence no special write is required to test for the complete short defect.
Referring again to FIG. 1a, to test for the above described leakage defect, a write operation is performed separately for each bit line for an adequately long duration, generally on the order of seconds, to guarantee that no such leakage defect exists. This is because leakage currents across FETs Q1 and Q2 can only be detected by "long write" operations in which bit lines BIT and BIT are written to for an extended period (i.e., long enough to allow a defective bit cell in the column to be discharged via leakage).
For example, if bit cell 100 has a capacitance C, and each of pull-up load resistors R1 and R2 has a resistance R, then the approximate duration of such a test is RC, assuming that, in the worst case, the defect indicates a leakage of the same magnitude as the pull-up load resistor current. In the case of a 256K SRAM organized as 256 rows.times.1024 columns, where columns of bit cells are accessed in groups of eight (i.e. eight columns for each word), 128 separate long write sequences are required to complete the test for the leakage defect failure mode. Each group of columns requires four test combinations (Store 0s, Long Write 1s; Store 1s, Long Write 0s; Store 0s, Long Write 0s; Store 1s, Long Write 1s) for a typical total test time of: EQU t=4YRC=1.5 seconds
wherein: PA1 R=10.sup.11 .OMEGA. PA1 C=30 fF (fF or femto F=10.sup.-15 F) (worst case) PA1 Y=1024 columns/8 bits=128 operations
Accordingly, a bottleneck to an efficient and fast throughput test for this leakage problem is an inability of a conventional SRAM to read or write more columns at a time. The total time required to verify that a typical SRAM is free from this type of defect is therefore significant. This problem will become more severe with increases in memory size in the future. A need therefore exists for a SRAM having addressing logic capable of performing "long write" operations simultaneously to more columns of memory bit cells than would be written to in a "write" operation during normal operation.